ESD suppression criteria for PCB design
PCB layout is a key element of ESD protection, and a reasonable PCB design can reduce the unnecessary cost of troubleshooting and rework. In PCB design, due to the use of transient voltage suppressor (TVS) diodes to suppress direct charge injection due to ESD discharge, it is more important in PCB design to overcome the electromagnetic interference (EMI) electromagnetic field effect generated by the discharge current. This article will provide PCB design guidelines that can optimize ESD protection.
Circuit loop
Current is induced into the circuit loop by induction, and these loops are closed and have varying magnetic flux. The magnitude of the current is proportional to the area of the ring. Larger loops contain more magnetic flux, which induces a stronger current in the circuit. Therefore, the loop area must be reduced.
The most common loop is shown in Figure 1, which is formed by the power supply and ground. Where possible, multilayer PCB designs with power and ground planes can be used. The multilayer board not only minimizes the loop area between the power supply and ground, but also reduces the high frequency EMI electromagnetic field generated by the ESD pulse.
If a multilayer board cannot be used, the wires for the power line and ground must be connected in a grid as shown in Figure 2. The grid connection can function as a power and ground plane. Use vias to connect the traces of each layer. The via connection spacing should be within 6 cm in each direction. In addition, when wiring, the power supply and ground traces as close as possible can also reduce the loop area, as shown in Figure 3.
Another way to reduce loop area and induce current is to reduce parallel paths between interconnected devices, see Figure 4.
A protective wire can be used when a signal cable longer than 30 cm must be used, as shown in FIG. A better approach is to place the formation near the signal line. When the signal line is used, it should be within 13 mm of the protection line or ground line.
As shown in Figure 6, the long signal line (>30 cm) or the power line of each sensitive component is placed across its ground line. Crossed lines must be arranged at regular intervals from top to bottom or left to right.
Circuit connection length
A long signal line can also be an antenna that receives ESD pulse energy. Using a shorter signal line as much as possible can reduce the efficiency of the signal line as an ESD electromagnetic field antenna.
Try to place the interconnected devices in adjacent locations to reduce the length of the interconnected traces.
Ground charge injection
Direct discharge of the ESD to the ground plane may damage sensitive circuitry. One or more high frequency bypass capacitors are also used while using the TVS diodes, which are placed between the power supply of the consumable component and ground. The bypass capacitor reduces charge injection and maintains the voltage difference between the power supply and the ground port.
The TVS shunts the induced current and maintains the potential difference of the TVS clamp voltage. TVS and capacitors should be placed as close as possible to the protected IC (see Figure 7). Ensure that the TVS to ground path and capacitor pin length are the shortest to reduce parasitic inductance effects.
The connector must be mounted to the copper-platinum layer on the PCB. Ideally, the copper-platinum layer must be isolated from the ground plane of the PCB and connected to the pad by a short line.
Other guidelines for PCB design
1. Avoid arranging important signal lines such as clocks and reset signals on the PCB edge;
2. Set the unused part of the PCB to the ground plane
3. The ground wire of the chassis and the signal line are at least 4 mm apart;
4. Keep the aspect ratio of the chassis ground wire less than 5:1 to reduce the inductance effect;
5. Use TVS diodes to protect all external connections;
Protection of parasitic inductance in the circuit
Parasitic inductance in the TVS diode path can cause severe voltage overshoot in the event of an ESD event. Despite the use of a TVS diode, an excessive overshoot voltage may still exceed the damage voltage threshold of the protected IC due to the induced voltage VL=L×di/dt across the inductive load.
The total voltage that the protection circuit is subjected to is the sum of the voltage generated by the TVS diode clamp voltage and the parasitic inductance, VT = VC + VL. An ESD transient induced current peaks in less than 1 ns (according to IEC 61000-4-2), assuming a lead inductance of 20 nH per inch, a line length of one-quarter inch, and an overshoot voltage of 50V /10A pulse. The empirical design rule is to minimize the parasitic inductance effect by designing the shunt path as short as possible.
All inductive paths must consider the ground loop, the path between the TVS and the protected signal line, and the path from the connector to the TVS device. The protected signal line should be connected directly to the ground plane. If there is no ground plane, the ground loop should be as short as possible. The distance between the ground of the TVS diode and the ground point of the protected circuit should be as short as possible to reduce the parasitic inductance of the ground plane.
Finally, the TVS device should be as close as possible to the connector to reduce transient coupling into nearby lines. Although there is no direct path to the connector, this secondary radiation effect can also cause malfunctions in other parts of the board.
PCB layout is a key element of ESD protection, and a reasonable PCB design can reduce the unnecessary cost of troubleshooting and rework. In PCB design, due to the use of transient voltage suppressor (TVS) diodes to suppress direct charge injection due to ESD discharge, it is more important in PCB design to overcome the electromagnetic interference (EMI) electromagnetic field effect generated by the discharge current. This article will provide PCB design guidelines that can optimize ESD protection.